`timescale 1ns/1ps

module id_fsm (
           input [7: 0] char,
           input clk,
           output out);

`define inError 2'b00
`define inChar 2'b01
`define inDigit 2'b10
`define digit_0 8'b0011_0000
`define digit_9 8'b0011_1001
`define char_A 8'b0100_0001
`define char_Z 8'b0101_1010
`define char_a 8'b0110_0001
`define char_z 8'b0111_1010

reg [1: 0]state;

initial begin
    state <= `inError;
end

function isChar;
    input [7: 0] char;
    begin
        isChar = (char >= `char_A && char <= `char_Z) || ((char >= `char_a && char <= `char_z));
    end
endfunction

function isDigit;
    input [7: 0] char;
    begin
       isDigit = char >= `digit_0 && char <= `digit_9;
    end
endfunction

always @(posedge clk) begin
    case (state)
        `inError: begin
            if (isChar(char)) begin
                state <= `inChar;
            end
            else begin
                state <= `inError;
            end
        end
        `inChar: begin
            if (isChar(char)) begin
                state <= `inChar;
            end
            else if (isDigit(char)) begin
                state <= `inDigit;
            end
            else begin
                state <= `inError;
            end
        end
        `inDigit: begin
            if (isChar(char)) begin
                state <= `inChar;
            end
            else if (isDigit(char)) begin
                state <= `inDigit;
            end
            else begin
                state <= `inError;
            end
        end
    endcase
end

assign out = (state == `inDigit) ? 1'b1 : 1'b0;

endmodule
